module tb_led( );
    reg sys_clk;
    reg rst;
    wire [3:0] led;
   led uu(sys_clk,rst,led );
   initial
   begin
              rst=1'b0; sys_clk=1'b0; 
       #100;  rst=1'b1;
   end
   always   #20 sys_clk= ~sys_clk;

endmodule